Back to Home

Approach & Methodology

A unified end-to-end AI framework for fully automated analog circuit design — from performance specification to layout generation.

Vision

Our Research Vision

Designing analog and RF circuits remains one of the most expertise-intensive and time-consuming challenges in modern electronics. The FALCON research program addresses this bottleneck by developing AI-driven methods for end-to-end analog circuit design, enabling the transition from specification to manufacturable layout.

Our work focuses on scalable learning-based models, large-scale datasets, and physics- and layout-aware optimization, with the goal of enabling reliable, generalizable design across diverse circuit topologies. By integrating data-driven modeling with domain knowledge and physical constraints, FALCON aims to establish a unified framework for efficient, scalable, and practical analog circuit design, bridging the gap between research innovation and real-world deployment.

🔍

Topology Selection

Selecting the optimal circuit architecture from a library of expert-designed topologies based on target performance specifications, guided by design heuristics.

⚙️

Parameter Optimization

Inferring circuit parameters using learned surrogate models to reduce reliance on expensive circuit simulations.

📐

Layout-Aware Design

Incorporating physical layout constraints, parasitics, and design rules directly into the optimization process.

🏭

Physical Synthesis

Translating optimized designs into manufacturable GDSII layouts through automated placement and routing.

Pipeline

End-to-End Design Pipeline

Our core framework unifies topology selection, forward modeling, and layout-aware inference into a single differentiable pipeline — the first to do so at industrial scale.

STAGE 1: Topology Selection Performance Spec y_target [Gain, NF, BW, P, ...] MLP Classifier Selected Topology T* STAGE 2: Forward Modeling Netlist to Graph Conversion Edge-Centric GNN + Differentiable Layout Cost STAGE 3: Layout-Aware Inference Gradient-Based Optimization x* + Differentiable Layout Cost Parasitic EM DRC Layout-Constrained Params
01

Topology Selection

A lightweight MLP classifier maps target performance specifications to the most suitable circuit topology from a curated library of 20 expert-designed architectures, guided by human design heuristics.

MLP Classifier · >99% Accuracy
02

Forward Performance Modeling

A custom edge-centric Graph Neural Network serves as a differentiable surrogate for the Cadence Spectre simulator, mapping netlist-derived circuit graphs to 16-dimensional performance vectors.

Edge-Centric GNN · 16-dim Output
03

Layout-Aware Inference

Gradient-based optimization over the learned GNN recovers design parameters satisfying target specs under a differentiable layout cost capturing parasitic effects, EM behavior, and DRC constraints.

Differentiable Layout · <1s Inference
Milestones

Key Results

Evaluated on 1M+ Cadence Spectre-simulated mm-wave circuits across 20 topologies.

🎯
>99%
Topology Selection
Accuracy
📊
<10%
Average Relative
Prediction Error
⚡
<1s
Design Time
Per Instance
🔬
20
Expert-Designed
Topologies

🏆 Research Contributions

  • ✓ First unified end-to-end framework for topology selection, parameter inference, and layout-aware optimization at industrial scale
  • ✓ Layout-constrained inverse design within a single differentiable pipeline
  • ✓ Largest foundry-grade analog circuit dataset: 1M+ Cadence-simulated circuits across 20 topologies
  • ✓ EM-aware physical synthesis for complete netlist-to-GDSII layout generation
  • ✓ Open-source code, datasets, and models under MIT license

⚙️ Technical Highlights

  • ✓ Sub-second inference on standard hardware (MacBook CPU)
  • ✓ Edge-centric GNN that generalizes to unseen topologies with minimal fine-tuning
  • ✓ 16-dimensional performance prediction covering gain, noise figure, bandwidth, power, and more
  • ✓ Comprehensive ML benchmarks across transformers, SVRs, random forests, and GNNs
  • ✓ Neural inductor modeling with EM-accurate predictions across 1–100 GHz