AIAS+ 2026  ·  Workshop  ·  November 6, 2026

Frontiers of AI-Driven Circuits, Chips & Semiconductors

A full-day workshop at the AI for Accelerated Science (AIAS+) 2026 Symposium bringing together leading researchers at the intersection of artificial intelligence and hardware design.

📅 Friday, November 6, 2026
📍 San Francisco, California
🏛️ AIAS+ 2026 Symposium
🔬 AI × Circuits × Semiconductors
Explore the Workshop ↓ Register Now ↗
About the Workshop

Where AI Meets Silicon

AI is poised to transform chip and semiconductor innovation across the full stack, from circuit discovery and architecture exploration to manufacturing, verification, and system-level optimization. As AI growth becomes increasingly constrained by hardware capacity and design complexity, accelerating semiconductor innovation has become central to the future of AI itself.

This full-day workshop, hosted as part of the AIAS+ 2026 Symposium — the Chen Institute Symposium for AI Advancing Science & Society (November 5–7, 2026, San Francisco, CA) — brings together researchers and practitioners advancing AI-driven chip design and semiconductor discovery. The workshop's primary focus is AI-native methodologies for electronic circuit and semiconductor system design, spanning physics-informed machine learning, graph neural networks, large-scale circuit datasets, and AI-assisted verification.

By uniting expertise across machine learning, circuit design, computer architecture, manufacturing, and scientific discovery, the workshop aims to catalyze a research community around AI-driven electronic and semiconductor systems, aligned with the AIAS+ 2026 vision of AI as a transformative partner in discovery.

🔬 AI for Analog/RF/Mixed-Signal Design

Physics-informed machine learning and graph neural networks for analog and RF circuit synthesis, topology selection, and performance prediction.

🧠 Physics-Informed & Knowledge-Driven Methods

Intelligent knowledge retrieval for design reuse, physics-aware models, and AI-assisted verification across the semiconductor stack.

📊 Datasets, Benchmarks & Foundation Models

Large-scale circuit datasets, standardized benchmarks, and foundation models enabling reproducible, scalable AI for hardware design.

🏭 Trustworthy & Scalable AI for Semiconductors

Broader AI methods for semiconductor materials, devices, manufacturing, packaging, and systems — with a focus on reliability and scalability.

Invited Speakers & Panelists

Speakers & Panelists

(more to come soon)

David Z. Pan
Professor of ECE · University of Texas at Austin
Kaushik Sengupta
Professor of ECE · Princeton University
Salman Avestimehr
Dean's Professor of ECE & CS · University of Southern California
Co-Founder · Teamily AI
Payam Heydari
Chancellor's Professor & Henry Samueli Faculty Excellence Professor of EECS & BME · University of California, Irvine
Boris Murmann
Professor of ECE · University of Hawaiʻi at Mānoa
Felicia Guo
Postdoctoral Researcher of EECS · University of California, Berkeley
Workshop Organizers

Organizing Committee

Hamidreza Aghasi
Associate Professor of EECS
University of California, Irvine
Amin Arbabian
Professor of EE
Stanford University
Salman Avestimehr
Dean's Professor of ECE & CS
University of Southern California
Workshop Schedule

Program

Time Session
10:10 – 12:10 Session 1 — Academic Talks & Panel
10:10 – 10:15
Opening Remarks
10:15 – 11:35
4 Invited Talks
11:35 – 12:10
Panel Discussion
12:10 – 14:00 ☕ Lunch Break
14:00 – 15:30 Session 2 — Industry Talks & Startup Highlights
14:00 – 15:00
3 Invited Industry Talks
15:00 – 15:30
4 Startup Highlights
Workshop Affiliation

Organized by the FALCON AI Lab

This workshop is organized by the FALCON AI Lab and held as part of the AIAS+ 2026 Symposium — the Chen Institute Symposium for AI Advancing Science & Society (November 5–7, 2026, San Francisco, CA).

🏛️ AIAS+ 2026 Symposium ↗ 🦅 FALCON AI Lab ↗